In semi-conductor components, more particularly memory components such as DRAMs (DRAM=Dynamic Random Access Memory and/or dynamic read/write memory) based on CMOS technology, so-called clock pulses are used for the chronological coordination of the processing and/or relaying of data.
Conventional semi-conductor components use one “single-ended” clock pulse—present on a single line—for this purpose.
The data may then for instance be relayed at any time by means of the ascending pulse flank of the single-ended clock pulse (or alternatively at any time for instance by means of the descending pulse flank of the single-ended clock pulse).
In conventional technology so-called DDR components, more particularly DDR-DRAMs (DDR-DRAM=double data rate DRAMs and/or DRAMs with a double data rate) are already well known.
In DDR-DRAMs, two differential, inverse clock pulses present on two separate lines are used, instead of one single clock pulse (“single ended” clock pulse) present on a single line.
Every time, for instance, when the first of the two clock pulses changes from a “high logic” state (i.e. a high voltage level) to a “low logic” state (i.e. a low voltage level), the second clock pulse—essentially simultaneously—changes its state from “low logic” to “high logic” (e.g. from a low to a high voltage level).
Conversely, whenever the first clock pulse changes from a state of “low logic” (e.g. from a low voltage level) to a state of “high logic” (e.g. a high voltage level), the second clock pulse (again essentially simultaneously) changes its state from “high logic” to “low logic” (e.g. from a high to a low voltage level).
With DDR-DRAMS, data is relayed by both the ascending flank of a particular clock pulse and the descending flank of the same clock pulse.
This means that data is relayed more frequently and/or faster (more particularly, twice as frequently and/or twice as fast) with a DDR-DRAM relaying the data, than with corresponding conventional DRAMs using “single ended” clock pulses; in other words the data rate of DDR-DRAMs is twice as high as that of corresponding conventional DRAMs.
DDR-DRAMs contain two pulse connections and in the normal operating mode of a DRAM, the above-mentioned first clock pulse—generated by an external clock pulse trigger—is applied to the first pulse connection of the DRAM, and the second clock pulse—also generated by the external clock pulse trigger but inverted in relation to the first clock pulse—is applied to the second clock pulse connection.
When the DDR-DRAM is tested before being put into use (i.e. when it is operated in test mode instead of in the normal operating mode)—for instance by means of a special external test apparatus—the relevant clock pulses, instead of being generated by an external clock pulse trigger, are generated by an external test apparatus and applied to the relevant DRAM connections.
Thereby the above-mentioned differential test clock pulse generated by the test apparatus—corresponding with the relevant differential clock pulse—can be applied to the corresponding first and second pulse connections of the DDR components, or alternatively the test apparatus may simply generate one single-ended test clock pulse, corresponding with a clock pulse from a current component using only one single clock pulse.
This single test clock pulse is, for example, simply applied to the first pulse connection of the DRAMs (at the second component pulse connection there will then be no (test) clock pulse present, but for instance a voltage, VREF; this voltage is needed for operating the DDR-DRAMs, i.e. it must be supplied by the test apparatus and may during the test be applied to the second pulse connection as well).
By using one single test clock pulse (instead of the above two inverted test clock pulses), test channels can be spared in the relevant test apparatus being used.
Apart from this, it becomes possible for a test apparatus designed for testing currently available components and using one single-ended clock pulse (or a similar and/or corresponding test apparatus) to be used for testing DDR-DRAMs designed to be tested by differential test clock pulses.